In order to overcome the pressing limitations of CMOS scaling in logic and memory applications, many alternative nanotechnologies have been proposed. Research in such alternative technologies has revealed that resistive memory elements, referred to herein as “memristors,” have various digital and analog applications in, for example, ultra-dense crossbar memories, configurable logic applications, and as synaptic connections in neuromorphic architecture. For purposes of illustration and clarity, the description below will be with respect to resistive memory elements in the form memristors. It will be appreciated by those having ordinary skill in the art, however, that the present disclosure is not meant to be limited to the use of such elements or devices, but rather any number of suitable resistive memory elements may be used and remain within the spirit and scope of the present disclosure.
A memristor may be comprised of a TiO2 thin film having two layers where the total resistance of the memristor is the sum of the resistances of the two layers. In an exemplary embodiment, one layer of the film has a high concentration of dopants and the other layer has a low (zero or virtually zero) concentration of dopants. The resistance of the memristor can be expressed and determined as set forth in equation (1):
                    R        =                                            w              D                        ⁢                          R              ON                                +                                    (                              1                -                                  w                  D                                            )                        ⁢                          R              OFF                                                          (        1        )            where w is the width of the doped region, D is the total length of the thin film, RON is the lowest resistance when w=D, and ROFF is the highest resistance when w=0. The rate of change of w with time
  (            i      .      e      .        ,                  dw        ⁡                  (          t          )                    dt        )is represented as shown in equation (2):
                                          dw            ⁡                          (              t              )                                dt                =                              μ            v                    ⁢                                    R              ON                        D                    ⁢                      i            ⁡                          (              t              )                                                          (        2        )            where μv is the dopant mobility and i(t) is the current passing through the memristor.
Memristors have been proposed to be used as non-volatile memory elements due to the fact that they retain their logical or resistive state even when they are un-powered. The resistive state of such devices indicates the data stored. For example, a memristor may store one bit of information or data where the low resistive state of the device can be represented as a logic “0” and the high resistive state can be represented as a logic “1.” Since the resistance change in these devices or elements follows a continuous path, more than one bit of data can be stored in a single memristor when the data is encoded as distinct resistive states.
In practice, memristors have been used in memory applications with or without series active devices such as, for example, diodes and transistors, which provide isolation during read or write operations. This difference mainly depends on the current characteristics of the particular memristive device or element used. A memristor with highly nonlinear characteristics may not need such extra devices for isolation.
The possibility of using memristors as parts of non-volatile memory cells has led to the development of read and write circuitries for memory structures, such as, for example, ultra-dense crossbar memory structures. In general terms, and as is known in the art, a crossbar memory structure includes a first array of parallel conductors (e.g., nanowires) (hereinafter referred to as “rows”) and a second array of parallel conductors (e.g., nanowires) (hereinafter referred to as “columns”), wherein the rows and columns are orientated at an angle with each other. The crossbar memory structure may further comprise a plurality of resistive memory elements (i.e., memristors), each one of which is respectively disposed between (i.e., at the intersection of) a single row and a single column of the crossbar memory structure. In each instance, the combination of the memristor and the conductors or wires of the corresponding row and column serves to form a resistive memory cell. Accordingly, a crossbar memory structure that includes a plurality of memristors disposed at respective intersections of the columns and rows of the crossbar memory structure comprises a plurality of resistive memory cells, each of which is disposed between a different row-column combination.
In crossbar memory structures such as that briefly described above, a single memory cell may be selected when the row and column of the crossbar memory structure corresponding thereto is selected. To select a row, a read, write, or erase voltage is applied to that particular row; and to select a column, a read, write, or erase voltage that is different than the voltage applied to the row is applied to that particular column. These voltages will be hereinafter referred to as “selection voltages.” Unselected rows and columns of the crossbar memory structure are biased with an “unselect voltage,” which is different than the selection voltages applied to the desired row and column.
With respect to the reading of the data stored in a memory cell, and the memristor thereof, in particular, most conventional methodologies use the same resistive state encoding to represent stored data. Examples of encodings for memory cells storing a single bit and two bits of data are illustrated in FIGS. 1A and 1B, respectively. One drawback of conventional crossbar memory structures is that read methodologies corresponding thereto typically include the use of multiple comparators to compare the resistivity of the selected memory cell against multiple reference resistors to determine the current state. Generally speaking, two comparisons are required for each possible state that the memory cell may assume to determine if the resistance of the memristor is in that particular state. More particularly, for each potential state, one comparison is required to determine if the resistance of the memristor is equal to or greater than the lower bound for the reference state, and a second comparison is required to determine if the resistance is equal to or less than the upper bound for that state. For example, in an instance wherein there is a single bit of stored data, the resistance of the memristor typically has to be compared to the lower bound of the “0” state, the upper bound of the “0” state, the lower bound of the “1” state, and the upper bound of the “1” state. Accordingly, for a memristor storing a single bit of data, four (4) comparisons are generally required. In an instance where a memristor stores two bits of data (as opposed to a single bit), the number of required comparisons doubles to eight (8), as the resistance of the memristor has to be compared to: the lower and upper bounds of the “00” state; the lower and upper bounds of the “01” state; the lower and upper bounds of the “10” state; and the lower and upper bounds of the “11” state. Accordingly, in order to determine the exact state for an n-bit memristor cell, theoretically 2(n+1) comparisons are needed since the current state of the memristor needs to be compared against the upper and lower bounds of all possible states; in practice, however, the actual number of required comparisons can be reduced to 2(n+1)−2 by omitting comparisons for the lower bound of the lowest state and the upper bound of the highest state. It will be appreciated that these comparisons may be omitted because these bounds represent the limits of the memristor. Accordingly, for a single n-bit memristor of a conventional crossbar memory structure, 2(n+1)−2 comparators and 2(n+1)−2 reference resistors (or sources) are needed to determine the exact state of the memristor in one cycle, which adds complexity and cost to the crossbar memory structure.
In addition to the drawbacks described above, further drawbacks of conventional crossbar memory structures relate to the effects of memory state dependence and parasitic resistances to which memory cells (memristors) thereof may be exposed. Memory state dependence may be a problem due to the fact that the leakage current through unselected memory cells in the crossbar memory structure may affect the value read when the total leakage current exceeds a certain magnitude. Parasitic resistances can result in different resistive values being stored in the cells for the same logical value.
Accordingly, there is a need for crossbar memory structures and/or components thereof that minimize and/or eliminate one or more of the above-identified deficiencies.